1. Field of the Invention
The present invention relates to an electronic parts packaging structure and a method of manufacturing the same and, more particularly, an electronic parts packaging structure capable of dealing easily with a reduction in thickness and a method of manufacturing the same.
2. Description of the Related Art
The development of the LSI technology as the key technology to actualize the multimedia device is proceeding steadily toward the higher speed and the larger capacity of the data transmission. Following this trend, the packaging technology serving as the interface between the LSI and the electronic device is advanced toward the higher density.
For instance, in Patent Literature 1 (Patent Application Publication (KOKAI) 2002-170840), it is set forth that, in order to connect electrically the printed-wiring board and the semiconductor chip without the intervention of the lead parts, the semiconductor chip is mounted in the recess portion of the integral type core substrate, in which the recess portion is provided, and then the multi-layered wiring that is connected to the semiconductor chip is formed thereon.
Also, in Patent Literature 2 (Patent Application Publication (KOKAI) 2000-323645), the semiconductor device having such a structure that a plurality of semiconductor chips are mounted three-dimensionally on the circuit board in a state that they are embedded in the insulating layer and a plurality of semiconductor chips are connected mutually via the wiring pattern, which is formed in a multi-layered fashion via the insulating layers, is set forth.
Meanwhile, in the semiconductor device in which the semiconductor chips are stacked three-dimensionally on the circuit board, the reduction of the total thickness as well as the miniaturization is requested.
In above Patent Literatures 1 and 2, no consideration is given to the reduction of the total thickness of the semiconductor device.